This week, Intel unveiled its\u00a0Xeon 6+ processors, code-named\u00a0Clearwater Forest, manufactured on the Intel 18A node, the firm\u2019s most advanced fabrication process and its first design in the 1.8-nanometer class.<\/p>\n
The launch highlights a shift in Intel\u2019s strategy for cloud and telecommunications workloads. Instead of prioritizing raw clock speeds, the company is focusing on efficiency, integration, and dense compute capacity.<\/p>\n
Clearwater Forest introduces Intel\u2019s new\u00a0Darkmont efficiency-core microarchitecture. A single processor can contain as many as\u00a0288 Darkmont cores, distributed across\u00a012 compute tiles. Each tile houses\u00a024 cores\u00a0built using the 18A process and connected through Intel\u2019s\u00a0Foveros Direct\u00a03D stacking technology.<\/p>\n
The chip\u2019s design relies heavily on advanced packaging. Communication between the different components is handled by\u00a0EMIB (Embedded Multi-Die Interconnect Bridge)\u00a0links, the same interconnect approach Intel uses in its high-end GPU products.<\/p>\n
A key objective of the architecture is to minimize latency and power consumption by keeping frequently used data close to the cores. To achieve this, Intel redesigned the cache structure. Groups of\u00a0four Darkmont cores share a 4 MB L2 cache, while the processor\u2019s last-level cache exceeds\u00a01.1 GB (approximately 1,152 MB), enabling hundreds of cores to access commonly used data without relying heavily on external memory bandwidth.<\/p>\n
Despite being built around efficiency cores, the Xeon 6+ platform integrates several accelerators commonly used in modern data-center workloads. These include\u00a0Intel Advanced Matrix Extensions (AMX)\u00a0for AI tasks,\u00a0QuickAssist Technology (QAT)\u00a0for compression and cryptography, and\u00a0vRAN Boost, designed for virtualized radio access networks.<\/p>\n
These capabilities target telecom and edge deployments supporting\u00a05G Advanced\u00a0and future\u00a06G\u00a0infrastructure. By embedding such accelerators directly into the CPU, Intel argues operators can scale AI inference and network processing without adding separate hardware cards.<\/p>\n
The platform remains compatible with the existing Xeon socket, simplifying upgrades. It supports\u00a012 channels of DDR5 memory up to 8,000 MT\/s\u00a0and provides\u00a096 PCIe 5.0 lanes, including\u00a064 lanes with CXL 2.0\u00a0support. In dual-socket servers, systems can scale up to\u00a0576 Darkmont cores.<\/p>\n","protected":false},"excerpt":{"rendered":"
This week, Intel unveiled its\u00a0Xeon 6+ processors, code-named\u00a0Clearwater Forest, manufactured on the Intel 18A node, the firm\u2019s most advanced fabrication process and its first design in the 1.8-nanometer class. The launch highlights a shift in Intel\u2019s strategy for cloud and telecommunications workloads. Instead of prioritizing raw clock speeds, the company is focusing on efficiency, integration, […]<\/p>\n","protected":false},"author":254,"featured_media":452203,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":[],"meta":{"_acf_changed":false,"_breakdance_hide_in_design_set":false,"_breakdance_tags":"","footnotes":""},"categories":[29330],"tags":[29372,29405,29418,29371],"audience-intent":[],"content-types":[],"country":[],"entity":[],"persona":[],"class_list":["post-452202","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-business","tag-electronics","tag-enterprise-news","tag-hardware","tag-semiconductors"],"acf":[],"_links":{"self":[{"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/posts\/452202","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/users\/254"}],"replies":[{"embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/comments?post=452202"}],"version-history":[{"count":0,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/posts\/452202\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/media\/452203"}],"wp:attachment":[{"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/media?parent=452202"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/categories?post=452202"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/tags?post=452202"},{"taxonomy":"audience-intent","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/audience-intent?post=452202"},{"taxonomy":"content-types","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/content-types?post=452202"},{"taxonomy":"country","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/country?post=452202"},{"taxonomy":"entity","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/entity?post=452202"},{"taxonomy":"format","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/format?post=452202"},{"taxonomy":"persona","embeddable":true,"href":"https:\/\/menatech.net\/en\/wp-json\/wp\/v2\/persona?post=452202"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}